What Verilator Does

Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multithreaded .cpp and .h files, the "Verilated" code.

These Verilated C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper file, to instantiate the Verilated model. Executing the resulting executable performs the design simulation. Verilator also supports linking Verilated generated libraries, optionally encrypted, into other simulators.

Verilator may not be the best choice if you are expecting a full-featured replacement for a closed-source Verilog simulator, need SDF annotation, mixed-signal simulation, or are doing a quick class project (we recommend Icarus Verilog for classwork). However, if you are looking for a path to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of designs, Verilator is the tool for you.

What is lint?
在 Verilator 中，lint 是指对 Verilog/SystemVerilog 代码进行静态代码分析 的过程，目的是在代码转换（生成 C++ 模型）之前，检测代码中的潜在错误、不规范的编码风格或可能导致仿真/综合问题的结构。它的作用类似于代码的“体检”，确保输入代码的质量和可靠性。

Ref: https://www.veripool.org/verilator/

main函数

// This is intended to be a minimal example.  Before copying this to start a
    // real project, it is better to start with a more complete example,
    // e.g. examples/c_tracing.

    // Construct a VerilatedContext to hold simulation time, etc.
    VerilatedContext* contextp = new VerilatedContext;

    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
    // This needs to be called before you create any model
    contextp->commandArgs(argc, argv);

    // Construct the Verilated model, from Vtop.h generated from Verilating "top.v"
    Vtop* top = new Vtop{contextp};

Vtop 是Verilator根据你的Verilog顶层模块（比如module top）自动生成的C++类
new Vtop 创建这个类的实例对象，并将Verilated的上下文对象传递给它
top 指针后续将用于访问你的Verilog设计的所有输入输出信号和内部状态

file structure:

ghhu@ysyx:~/Desktop/study/verilator_test/mytest$ tree
.
├── obj_dir
│   ├── sim_main.d
│   ├── sim_main.o
│   ├── verilated.d
│   ├── verilated.o
│   ├── verilated_threads.d
│   ├── verilated_threads.o
│   ├── Vtop
│   ├── Vtop___024root__DepSet_h84412442__0.cpp
│   ├── Vtop___024root__DepSet_h84412442__0__Slow.cpp
│   ├── Vtop___024root__DepSet_heccd7ead__0.cpp
│   ├── Vtop___024root__DepSet_heccd7ead__0__Slow.cpp
│   ├── Vtop___024root.h
│   ├── Vtop___024root__Slow.cpp
│   ├── Vtop__ALL.a
│   ├── Vtop__ALL.cpp
│   ├── Vtop__ALL.d
│   ├── Vtop__ALL.o
│   ├── Vtop_classes.mk
│   ├── Vtop.cpp
│   ├── Vtop.h
│   ├── Vtop.mk
│   ├── Vtop__Syms.cpp
│   ├── Vtop__Syms.h
│   ├── Vtop__ver.d
│   └── Vtop__verFiles.dat
├── sim_main.cpp
└── top.v

1 directory, 27 files

举个通俗的比喻：假设你有一个Verilog电路设计图纸（top.v），Verilator就像一个翻译器，把这个图纸转换成了C++的乐高积木套装（Vtop.h）。

verilator Getting Started

What Verilator Does